Due to their high circuit density, input and output (I/O) connectivity to memory arrays presents significant challenges. In particular, routing lines to and from the memory array becomes difficult as the chip area needed for connections to the array is likely to occupy a large portion of the array area. When such space requirements are multiplied by the number of access points desired on the array, it becomes apparent that the array's density suffers.
In a similar manner, lines within the memory array are also constrained as to their dimensions, particularly their width. Narrow memory array lines impede performance of the memory array as the narrow lines will exhibit excessively high resistivity due to the confined cross-sectional area of the lines themselves. The high resistivity and ohmic loss of the memory array lines combined with the expected programming and erase voltage levels propagating along them creates significant power dissipation and heat. The large amount of power dissipated in the memory array lines will require a higher applied voltage in order to compensate for the array line losses. Furthermore, the propagation delay accompanying the high resistivity of the array lines should be taken into account. In particular, the lines' high resistance results in a significant propagation delay of the applied signals along the array lines to the memory cells, as the R-C (resistance-capacitance) time constant is defined in part by cumulative resistance of array lines. A long propagation delay of the applied signal is deleterious in achieving fast programming, erase, and read operations for the memory cells. Widening or broadening the array lines to reduce the lines' series resistance is not possible in a space-limited, high density array.
Another conventional technique, stitching, in which additional conductive lines are connected to the array line, is also not space efficient, particularly at the high voltage levels seen in non-volatile arrays.
Salicidation represents another conventional process by which array lines are treated to become more conductive, although the level of improvement is rather small.
Accordingly, what is needed is a means by which the resistance of array lines in a high density, non-volatile memory array is reduced.